深圳市伟格兴电子科技有限公司
单价:电议品牌:原厂封装:SMD/DIP货期:现货年份:2019包装:原厂标准电压:2.5V电流:0.003
深圳市伟格兴电子科技有限公司是一家大型集成电路代理,分销商,公司在深圳.作为的集成电路分销商,我公司拥有丰富经验的IC销售人员,为客户提供全面的服务支持。我公司主要从事美国ADI、MAXIM,TI,ON,ST,FAIRCHILD,ADI,NXP等世界的IC和功率模块 GTR、IGBT、IPM、PIM可控硅 整流桥 二极管等,涵盖通信、半导体、仪器仪表、航天航空、计算机及周边产品、消费类电子等广泛领域。公司多,价格合理。经过我公司全体人员的共同努力, 深圳市伟格兴电子科技有限公司现已成为国有大、中型企业,企业,中小型分销商的可靠合作伙伴,业务遍及中国大陆及海外市场。 我公司在国外拥有直接的货源和存货,与**上享有良好声誉的大量供应商建立了良好的长期合作关系。定货渠道好,周期短,以‘交货快捷、质量**、价格合理’为服务的宗旨,**所提供货品均为原包装。 我公司一贯坚持:“品质、服务至上”的发展宗旨以向用户提供系统 免费技术解决方案和满意的服务为己任。我们希望结交更多的合作伙伴,以合理的价格、的服务,与大家共同开创广阔的未来!同时也希望与业界**进行广泛的交流与合作,共同为电子业繁荣发展作出自己的贡献!
Security Level: Confidential A - 12 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
ORDERING GUIDE
Part Number Temperature Range Package Description Package Option
SSD102 -40°C to +85°C LQFP 100-pin
MARKING INFORMATION
SSD102
DISCLAIMER
SIGMASTAR TECHNOLOGY RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE
TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO
RESPONSIBILITY IS ASSUMED BY SIGMASTAR TECHNOLOGY ARISING OUT OF THE APPLICATION
OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Electrostatic charges accumulate on both test equipment and human body and can discharge without
detection. SSD102 comes with ESD protection circuitry; however, the device may be permanently
damaged when subjected to high energy discharges. The device should be handled with proper ESD
precautions to prevent malfunction and performance degradation.
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芯智**有限公司
Internal Use Only
Security Level: Confidential A
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
REGISTER DESCRIPTION
General Control Register
General Control Register
Index Name Bits Description
00h
REGBK 7:0 Default : 0x00 Access : R/W
XTAL_OK (RO) 7 Crystal ready.
MCU_SEL (RO) 6 0: Embedded MCU.
1: External serial bus interface.
- 5:4 Reserved.
AINC 3 Serial bus address auto Increase.
0: Enable.
1: Disable.
- 2 Reserved.
REGBK[1:0] 1:0 Register Bank Select.
00: Register of scaler.
01: Register of ADC/ACE/MCU.
10: Register of Video Decoder Front End (VFE).
11: Register of Video Decoder 2D Comb Filter (VCF).
REGBK[2:0] 2:0 Register Bank Select.
000: Register of scaler.
001: Register of ADC/ACE/MCU.
010: Register of Video Decoder Front End (VFE).
011: Register of Video Decoder 2D Comb Filter (VCF)
01h ~
FFh
- 7:0 Default : - Access : -
- 7:0 Reserved.
Scaler Register (Bank = 00, Registers 01h ~ 9Fh)
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
01h
DBFC 7:0 Default : 0x80 Access : R/W
- 7:3 Reserved.
DBL[1:0] 2:1 Double Buffer Load.
00: Keep old register value.
01: Load new data (auto reset to 00 when load finish).
10: Automatically load data at VSYNC blanking.
11: Reserved.
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Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
DB_EN 0 Double Buffer Enable.
0: Disable.
1: Enable.
02h ISELECT 7:0 Default : 0x00 Access : R/W
NIS 7 No Input Source.
0: Input source active.
1: Input source inactive, output is free-run.
STYPE[1:0] 6:5 Input Sync Type.
00: Auto detected.
01: Input is separated HSYNC and VSYNC.
10: Input is Composite sync.
11: Input is sync-on-green (SOG).
COMP 4 CSYNC/SOG select (only useful when STYPE = 00).
0: CSYNC.
1: SOG.
ICS 3 Input Color Space.
0: RGB.
1: YCbCr.
IHSU 2 Input Sync Usage.
When EXTVD=0:
0: Use HSYNC to perform mode detection, HSOUT from ADC to
sample pixel.
1: Use HSYNC only.
When EXTVD=1:
0: Normal.
1: Output black at blanking.
BYPASSMD 1 By-Pass Mode for interlace-input-interlace-output.
EXTVD 0 0: Select analog input (CVBS/S-Video/RGB/YCbCr).
1: Select digital input (CCIR656).
03h IPCTRL2 7:0 Default : 0x18 Access : R/W
VDS_EN 7 Input data double sample
In CCIR input mode,
0: for horizontal output resolution less than 720 pixels.
1: for horizontal output resolution more than 720 pixels.
In analog input mode,
0: half sample of input data.
1: original sample of input data.
SSD102
Smart HD Display Controller
Preliminary Data Sheet Version 0.1
Security Level: Confidential A - 4 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
GENERAL DESCRIPTION
The SSD102 is a high quality ASIC for NTSC/PAL/SECAM car TV application. It receives analog
NTSC/PAL/SECAM CVBS and S-Video inputs from TV tuners, DVD or VCR sources, including weak and distorted
**s, as well as analog YCbCr input from HDTV/SDTV systems. Automatic gain control (AGC) and 10-bit
3-channel A/D converters provide high resolution video quantization. With automatic video source and mode
detection, users can easily switch and adjust variety of ** sources. Multiple internal adaptive PLLs precisely
extract pixel clock from video source and perform sharp color demodulation. Built-in line-buffer supports
adaptive 2-D comb-filter, 2-D sharpening, and synchronization stabler in a condense manner. The output for
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
VDS_MTHD 6 Input data double sample Method.
0: Using average.
1: Using advance GT filter.
IVDS 5 Input VSYNC Delay Select.
0: Delay 1/4 input HSYNC (recommended).
1: No delay.
HES 4 Input HSYNC reference Edge Select.
0: From HSYNC leading edge, default value.
1: From HSYNC tailing edge.
VES 3 Input VSYNC reference Edge Select.
0: From VSYNC leading edge, default value.
1: From VSYNC tailing edge.
ESLS 2 Early Sample Line Select.
0: 8 lines.
1: 16 lines.
VWRP 1 Input image Vertical Wrap.
0: Disable.
1: Enable.
HWRP 0 Input image Horizontal Wrap.
0: Disable.
1: Enable.
04h ISCTRL 7:0 Default : 0x10 Access : R/W
DDE 7 Direct DE mode for CCIR input.
0: Disable direct DE.
1: Enable direct DE.
DEGR[2:0] 6:4 DE or HSYNC post Glitch removal Range.
HSFL 3 Input HSYNC Filter.
0: Filter off.
1: Filter on.
ISSM 2 Input Sync Sample Mode.
0: Normal.
1: Glitch-removal.
MVD_SEL 1:0 MVD mode Select
0: CVBS.
1: S-Video.
2: YCbCr.
3: RGB.
05h SPRVST_L 7:0 Default : 0x10 Access : R/W, DB
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Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
SPRVST[7:0] 7:0 Image vertical sample start point, count by input HSYNC (lower 8
bits).
06h SPRVST_H 7:0 Default : 0x00 Access : R/W, DB
- 7:3 Reserved.
SPRVST[10:8] 2:0 Image vertical sample start point, count by input HSYNC (higher 3
bits).
07h SPRHST_L 7:0 Default : 0x01 Access : R/W, DB
SPRHST[7:0] 7:0 Image horizontal sample start point, count by input dot clock
(lower 8 bits).
08h SPRHST_H 7:0 Default : 0x00 Access : R/W, DB
- 7:4 Reserved.
SPRHST[11:8] 3:0 Image horizontal sample start point, count by input dot clock
(higher 4 bits).
09h SPRVDC_L 7:0 Default : 0x10 Access : R/W, DB
SPRVDC[7:0] 7:0 Image vertical resolution (vertical display enable area count by
line; lower 8 bits).
0Ah SPRVDC_H 7:0 Default: 0x00 Access : R/W
- 7:3 Reserved.
SPRVDC[10:8] 2:0 Image vertical resolution (vertical display enable area count by
line; higher 3 bits).
0Bh SPRHDC_L 7:0 Default : 0x10 Access : R/W
SPRHDC[7:0] 7:0 Image horizontal resolution (horizontal display enable area count
by pixel; lower 8 bits).
0Ch SPRHDC_L 7:0 Default : 0x00 Access : R/W
- 7:3 Reserved.
SPRHDC[11:8] 3:0 Image horizontal resolution (horizontal display enable area count
by pixel; higher 4 bits).
0Dh LYL 7:0 Default : 0x00 Access : R/W
- 7:4 Reserved.
LYL[3:0] 3:0 Lock Y Line.
0Eh INTLX 7:0 Default : 0x00 Access : -
ITU_EXT_FIELD 7 Using External FIELD for ITU interface.
SSD102
Smart HD Display Controller
Preliminary Data Sheet Version 0.1
Security Level: Confidential A - 10 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
MECHANICAL DIMENSIONS
E
E1
Symbol
Millimeter Inch
Min. Nom. Max. Min. Nom. Max.
A - - 1.6 - - 0.063
A1 0.05 - 0.15 0.002 - 0.006
A2 1.35 1.4 1.45 0.053 0.055 0.057
D 15.8 16 16.2 0.622 0.630 0.638
D1 13.8 14 14.2 0.543 0.551 0.559
E 15.8 16 16.2 0.622 0.630 0.638
E1 13.8 14 14.2 0.543 0.551 0.559
b 0.17 0.2 0.27 0.007 0.008 0.011
e 0.42 0.5 0.58 0.017 0.020 0.023
Sigmastar Confidential for
芯智**有限公司
Internal Use Only
SSD102
Smart HD Display Controller
Preliminary Data Sheet Version 0.1
Security Level: Confidential A - 11 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Symbol Min Max Units
3.3V Supply Voltages V VDD_33 3.63 V
1.2V Supply Voltages V VDD_12 1.32 V
Input Voltage (5V tolerant inputs) V IN5Vtol 5.0 V
Input Voltage (non 5V tolerant inputs) V IN V DD_33 V
Ambient Operating Temperature
T A -40 85
°C
Storage Temperature T STG -40 125 °C
Junction Temperature T J 125 °C
Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only and does not imply functional operation of the device. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Sigmastar Confidential for
芯智**有限公司
Internal Use Only
SSD102
Smart HD Display Controller
Preliminary Data Sheet Version 0.1
Security Level: Confidential A - 12 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
ORDERING GUIDE
Part Number Temperature Range Package Description Package Option
SSD102 -40°C to +85°C LQFP 100-pin
MARKING INFORMATION
SSD102
DISCLAIMER
SIGMASTAR TECHNOLOGY RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE
TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO
RESPONSIBILITY IS ASSUMED BY SIGMASTAR TECHNOLOGY ARISING OUT OF THE APPLICATION
OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Electrostatic charges accumulate on both test equipment and human body and can discharge without
detection. SSD102 comes with ESD protection circuitry; however, the device may be permanently
damaged when subjected to high energy discharges. The device should be handled with proper ESD
深圳伟格兴电子,地处亚太深圳。诚信13年合作伙伴。原装质量**。只做原装!
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联系手机是13686456875,
主要经营专业的集成电路分销商,我公司拥有丰富经验的IC销售人员,为客户提供全面的服务支持。我公司主要从事美国ADI、MAXIM,TI,ON,ST,FAIRCHILD,ADI,NXP等世界**品牌的IC和功率模块 GTR、IGBT、IPM、PIM可控硅 整流桥 二极管等,涵盖通信、半导体、仪器仪表、航天航空、计算机及周边产品、消费类电子等广泛领域。公司现货多,价格合理。。
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